LAB UART [temp]

การทดลองที่ 6

Serial UART

อุปกรณ์

1. บอร์ด Altena Cyclone III                                                                                                        1 บอร์ด

2. สายดาวน์โหลด ByteBlaster II Cable หรือ สายดาวน์โหลดUSB Blaster Cable                                1 ชุด

3. เครื่องคอมพิวเตอร์(Quatus II web edition)                                                                           

4. ออสซิลโลสโคป                                                                                                                      1เครื่อง

5. โปรแกรม Putty       
          

โจทย์

สร้างวงจรดิจิทัลเพื่อส่งตัวอักษร 'a' ผ่าน UART ไปยังคอมพิวเตอร์ เมื่อกดปุ่มแล้วปล่อยในแต่ละครั้ง โดยใช้ค่า baudrate เท่ากับ 9600 (เน้นส่งข้อมูลไบต์จาก FPGA ไปยังคอมพิวเตอร์เท่านั้น ยังไม่ต้องรับข้อมูล)

Source Code 

โค๊ด  component_debounce

library ieee; library work; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity component_debounce is generic( DELAY: integer :=20000 ); port( CLK, PB : in std_logic; signal_out : out std_logic ); end component_debounce; architecture Behavior of component_debounce is signal debounce,latch: integer:=0; signal pressed,signal_sent: std_logic:='1'; begin process (CLK, PB) begin if rising_edge(CLK) then if(PB = '1')then debounce <= 0; latch <= latch + 1; if latch > 10000 then signal_sent <= '1'; end if; else debounce <= debounce + 1; latch <= 0; end if; if(debounce > DELAY)then pressed <= '1'; end if; if(pressed = '1')and(PB = '1')then signal_sent <= '0'; pressed <= '0'; end if; end if; end process; signal_out <= signal_sent; end Behavior;

โค๊ด uart_lib

--===========================================================================-- -- -- S Y N T H E Z I A B L E miniUART C O R E -- -- www.OpenCores.Org - January 2000 -- This core adheres to the GNU public license -- -- Design units : UART_Def -- -- File name : uart_lib.vhd -- -- Purpose : Implements an miniUART device for communication purposes -- between the OR1K processor and the Host computer through -- an RS-232 communication protocol. -- -- Library : uart_lib.vhd -- -- Dependencies : IEEE.Std_Logic_1164 -- --===========================================================================-- ------------------------------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- 0.1 Ovidiu Lupas 15 January 2000 New model -- olupas@opencores.org ------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- package UART_Def -------------------------------------------------------------------------------- library IEEE,STD; use IEEE.Std_Logic_1164.all; use IEEE.Numeric_Std.all; --**-- package UART_Def is ----------------------------------------------------------------------------- -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB -- Error message for unknowns (U, X, W, Z, -), converted to 0 -- Verifies whether vector is too long (> 16 bits) ----------------------------------------------------------------------------- function ToInteger ( Invector : in Unsigned(3 downto 0)) return Integer; end UART_Def; --==================== End of package header ======================-- package body UART_Def is function ToInteger ( InVector : in Unsigned(3 downto 0)) return Integer is constant HeaderMsg : String := "To_Integer:"; constant MsgSeverity : Severity_Level := Warning; variable Value : Integer := 0; begin for i in 0 to 3 loop if (InVector(i) = '1') then Value := Value + (2**I); end if; end loop; return Value; end ToInteger; end UART_Def; --================ End of package body ================--

โค๊ด UART_comp

library ieee,work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity UART_comp is port ( CLK : in Std_Logic; -- System Clock -- Rx : out Std_Logic; -- Control signal TxOut : out Std_Logic; -- Control signal PB : in Std_Logic:= '1'; Reset : in Std_Logic); -- Reset input end entity; --================== End of entity ==============================-- architecture Behaviour of UART_comp is component clkUnit port( SysClk : in Std_Logic; -- System Clock EnableRx : out Std_Logic; -- Control signal EnableTx : out Std_Logic; -- Control signal Reset : in Std_Logic -- Reset input ); end component; component component_debounce generic( DELAY: integer :=20000 ); port( CLK, PB : in std_logic; signal_out : out std_logic ); end component; signal tx_rdy : std_logic :='1'; --indicator signal t_tx : Std_Logic:= '0'; --buffer type tx_state_type is (IDLE,START,SEND,STOP); --state signal state : tx_state_type :=IDLE; signal s_stop,t_sig: std_logic:= '0'; --stop sending signal s_start : std_logic; -- still sending signal s_sent : std_logic:='1'; -- still sending signal data_count : integer :=0; --array counter signal s_EnableRx,s_EnableTx : std_logic; -- tx/rx tick signal signal data_out :std_logic_vector (7 downto 0):=(x"41"); --designed data out signal data_1 :std_logic_vector (7 downto 0):=(x"01"); --designed data out begin cmp1_inst: clkUnit port map(SysClk => CLK, EnableRx => s_EnableRx, EnableTx => s_EnableTx ,Reset => Reset ); --end generate; cmp2_inst: component_debounce port map(CLK => CLK, PB => PB,signal_out => s_sent); process (CLK , Reset) begin if Reset = '0' then state <= idle; t_tx <='1'; data_out <= x"41"; elsif rising_edge(CLK) then case state is when IDLE => s_stop <= '0'; s_start <= '0'; t_tx <= '1'; if s_sent = '0' then if s_EnableTx = '1' then t_tx <= '0'; state <= START; s_start <= '1'; end if; else state <= IDLE; end if; when START => if s_start = '1' then state <= SEND; else state <= START; end if; when SEND => s_start <= '0'; if s_EnableTx = '1' then if s_stop = '0' and data_count < 8 then t_Tx <= data_out(data_count); if t_sig = '1' then data_count <= data_count +1; t_sig <='0'; end if; elsif data_count >= 8 then t_tx <= '1'; s_stop <= '1'; state <= STOP; end if; else state <= SEND; t_sig <= '1'; end if; when STOP => data_count <= 0; if s_EnableTx = '1' then if s_stop = '1' then t_tx <= '1'; s_stop <= '0'; else state <= IDLE; data_out <= data_out + "1"; end if; else state <= STOP; end if; end case; end if; end process; TXout <= t_TX; end Behaviour; --==================== End of architecture ===================--

โค๊ด TB_UART_comp

library ieee; library work; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity TB_UART_comp is end TB_UART_comp; architecture testbench of TB_UART_comp is component UART_comp is port( CLK,Reset,PB : in std_logic; TxOut : out std_logic ); end component; signal t_CLK,t_Reset,t_TxOut,t_PB: std_logic; begin inst:UART_comp port map (CLK => t_CLK, Reset => t_Reset, TxOut=> t_TxOut ,PB =>t_PB ); process begin -- a process for generating the clock signal (50MHz) t_CLK <= '1'; wait for 10 ns; t_CLK <= '0'; wait for 10 ns; end process; process begin -- a process for generating the clock signal (50MHz) t_PB <= '1'; wait for 2 ms; t_PB <= '0'; wait for 2 ms; t_PB <= '1'; wait for 2 ms; t_PB <= '0'; wait for 2 ms; wait; end process; process begin t_Reset <= '1'; wait for 5 ms;t_Reset <= '0'; wait for 1 ms;t_Reset <= '1'; wait; end process; end testbench;

โค๊ด ClkUnit

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; ------------------------------------------------------------------------------- -- Baud rate generator ------------------------------------------------------------------------------- entity ClkUnit is port ( SysClk : in Std_Logic; -- System Clock EnableRx : out Std_Logic; -- Control signal EnableTx : out Std_Logic; -- Control signal Reset : in Std_Logic); -- Reset input end entity; --================== End of entity ==============================-- ------------------------------------------------------------------------------- -- Architecture for Baud rate generator Unit ------------------------------------------------------------------------------- architecture Behaviour of ClkUnit is ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- signal ClkDiv32 : Std_Logic; signal tmpEnRX : Std_Logic; signal tmpEnTX : Std_Logic; signal Cnt32,Cnt10,Cnt16 : integer:=0; begin ----------------------------------------------------------------------------- -- Divides the system clock of 50 MHz by 32 ----------------------------------------------------------------------------- process(SysClk,Reset) begin if Rising_Edge(SysClk) then if Reset = '0' then Cnt32 <= 0; ClkDiv32 <= '0'; else Cnt32 <= Cnt32 + 1; if Cnt32 = 32 then ClkDiv32 <= '1'; Cnt32 <= 0; -- 26 ns? else ClkDiv32 <= '0'; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- Provides the EnableRX signal, at ~ 155 KHz ----------------------------------------------------------------------------- process(SysClk,Reset) begin if Rising_Edge(SysClk) then if Reset = '0' then Cnt10 <= 0; tmpEnRX <= '0'; elsif ClkDiv32 = '1' then Cnt10 <= Cnt10 + 1; end if; if Cnt10 = 10 then tmpEnRX <= '1'; Cnt10 <=0; else tmpEnRX <= '0'; end if; end if; end process; ----------------------------------------------------------------------------- -- Provides the EnableTX signal, at 9.6 KHz ----------------------------------------------------------------------------- process(SysClk,Reset) begin if Rising_Edge(SysClk) then if Reset = '0' then Cnt16 <= 0; tmpEnTX <= '0'; elsif tmpEnRX = '1' then Cnt16 <= Cnt16 + 1; end if; if Cnt16 = 15 then tmpEnTX <= '1'; Cnt16 <= Cnt16 + 1; elsif Cnt16 = 17 then Cnt16 <= 0; tmpEnTX <= '0'; else tmpEnTX <= '0'; end if; end if; end process; EnableRX <= tmpEnRX; EnableTX <= tmpEnTX; end Behaviour; --==================== End of architecture ===================--

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