Keypad 4*4 FPGA

การทดลองที่ 5

Keypad 4*4  FPGA 

อุปกรณ์

1. บอร์ด Altena Cyclone III                                                                                                        1 บอร์ด

2. สายดาวน์โหลด ByteBlaster II Cable หรือ สายดาวน์โหลดUSB Blaster Cable                                1 ชุด

3. เครื่องคอมพิวเตอร์(Quatus II web edition)                                                                           

4. ออสซิลโลสโคป                                                                                                                      1 เครื่อง

5. Keypad 4*4                                                                                                                                      1 ชุด

โจทย์

 สร้างวงจรดิจิทัลเพื่ออ่านค่าจาก 4x4 keypad แล้วแสดงผลด้วย LEDs 

Source Code VHDL

โค๊ด  com_fsm_keypad 

library ieee; library work; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity com_fsm_keypad is generic( keyNumber : integer := 16; keyLoop : integer := 4; keyPressed : integer := 16 ); port( CLK ,input_reset,input_loop_change : in std_logic; input_detect : in std_logic_vector (keyLoop-1 downto 0); input_loop_out : out std_logic_vector(keyLoop-1 downto 0); -- data_out : out std_logic_vector (keyPressed-1 downto 0):=x"0000"; data_bin : out std_logic_vector (keyLoop-1 downto 0):=x"0" ); end com_fsm_keypad; architecture FSM of com_fsm_keypad is type key_loop is array (0 to keyLoop-1) of std_logic_vector(keyLoop-1 downto 0); constant row_loop : key_Loop :=( 0 => b"0111" , 1 => b"1011", 2 => b"1101" , 3 => b"1110"); type key_pressed is array (0 to keyPressed-1) of std_logic_vector(keyLoop-1 downto 0); constant data_out_t : key_pressed :=( 0 => b"0000" , 1 => b"0001" , 2 => b"0010" , 3 => b"0011" , 4 => b"0100" , 5 => b"0101" , 6 => b"0110" , 7 => b"0111" , 8 => b"1000" , 9 => b"1001" , 10=> b"1010" , 11=> b"1011" , 12=> b"1100" , 13=> b"1101" , 14=> b"1110" , 15=> b"1111" ); -- type key_detected is array (0 to keyPressed-1) of std_logic_vector(keyPressed-1 downto 0); -- constant key_detected_t : key_detected :=( -- 0 => b"0000" , -- 1 => b"0001" , 2 => b"0010" , 3 => b"0100" ,4 => b"1000" , -- 5 => b"0011" , 6 => b"0101" , 7 => b"0110" ,8=> b"1010" , 9 => b"1001" , 10=> b"1100" , -- 11 => b"0111" , 12=> b"1011" , 13=> b"1101" ,14=> b"1110" , -- 15=> b"1111" ); type state_type is (S0,S1,S2,S3); signal state : state_type :=S0; signal row_loop_t: std_logic_vector(keyLoop-1 downto 0):=row_loop(0); signal data_t : std_logic_vector(keyPressed-1 downto 0):= x"0000"; signal delay : integer := 0; signal data_bin_t:std_logic_vector (keyLoop-1 downto 0):=x"0"; signal pressed,state_pressed,loop_changed: std_logic :='1'; begin process (CLK, input_detect,input_reset) begin if input_reset = '0' then state <= S0; delay <=0; row_loop_t <= b"0111"; elsif rising_edge(CLK) then case state is when S0 => row_loop_t <= row_loop(0); loop_changed <='0'; if delay > 100000 then delay <= 0; pressed <= '0'; loop_changed <='1'; state <= S1; else delay <= delay + 1; end if; if loop_changed = '0' then if input_detect(3) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(0); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(2) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(1); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(1) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(2); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(0) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(3); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; end if; when S1 => row_loop_t <= row_loop(1); loop_changed <='0'; if delay > 100000 then delay <= 0; pressed <= '0'; loop_changed <='1'; state <= S2; else delay <= delay + 1; end if; if loop_changed = '0' then if input_detect(3) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(4); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(2) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(5); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(1) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(6); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(0) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(7); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; end if; when S2 => row_loop_t <= row_loop(2); loop_changed <='0'; if delay > 100000 then delay <= 0; pressed <= '0'; loop_changed <='1'; state <= S3; else delay <= delay + 1; end if; if loop_changed = '0' then if input_detect(3) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(8); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(2) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(9); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(1) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(10); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(0) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(11); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; end if; when S3 => row_loop_t <= row_loop(3); loop_changed <='0'; if delay > 100000 then delay <= 0; pressed <= '0'; loop_changed <='1'; state <= S0; else delay <= delay + 1; end if; if loop_changed = '0' then if input_detect(3) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(12); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(2) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(13); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(1) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(14); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; if input_detect(0) = '0' and state_pressed = '0' then --data_t(0) <= '1'; state_pressed <= '1'; data_bin_t <= data_out_t(15); else state_pressed <= '0'; data_t(0) <= '0'; -- data_bin_t <= data_out_t(0); end if; end if; end case; if(input_loop_change ='0')then if delay > 100000 then delay <= 0; pressed <= '0'; else delay <= delay + 1; end if; end if; end if; end process; input_loop_out <= row_loop_t; -- data_out <= data_t; data_bin <= data_bin_t; end FSM;

ผลการทดลอง

LAB 16X2 LCD screen

การทดลองที่ 4

16*2 LCD screen

อุปกรณ์

1. บอร์ด Altena Cyclone III                                                                                                        1 บอร์ด

2. สายดาวน์โหลด ByteBlaster II Cable หรือ สายดาวน์โหลดUSB Blaster Cable                                1 ชุด

3. เครื่องคอมพิวเตอร์(Quatus II web edition)                                                                           

4. ออสซิลโลสโคป                                                                                                                      1เครื่อง

โจทย์

ใช้ IP core สำหรับ 16x2 LCD ที่มีอยู่บนบอร์ด FPGA เพื่อแสดงข้อความ 
"Hello World!"

Source Code VHDL

โค๊ด  lcd16x2_ctrl

------------------------------------------------------------------------------- -- Title : 16x2 LCD controller -- Project : ------------------------------------------------------------------------------- -- File : lcd16x2_ctrl.vhd -- Author : <stachelsau@T420> -- Company : -- Created : 2012-07-28 -- Last update: 2012-11-28 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: The controller initializes the display when rst goes to '0'. -- After that it writes the contend of the input signals -- line1_buffer and line2_buffer continously to the display. ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2012-07-28 1.0 stachelsau Created ------------------------------------------------------------------------------- library ieee,work; use ieee.std_logic_1164.all; entity lcd16x2_ctrl is generic ( CLK_PERIOD_NS : positive := 20); -- 50MHz port ( clk : in std_logic; rst : in std_logic; lcd_e : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic; lcd_db : out std_logic_vector(7 downto 4); line1_buffer : in std_logic_vector(127 downto 0); -- 16x8bit line2_buffer : in std_logic_vector(127 downto 0)); end entity lcd16x2_ctrl; architecture rtl of lcd16x2_ctrl is constant DELAY_15_MS : positive := 15 * 10**6 / CLK_PERIOD_NS + 1; constant DELAY_1640_US : positive := 1640 * 10**3 / CLK_PERIOD_NS + 1; constant DELAY_4100_US : positive := 4100 * 10**3 / CLK_PERIOD_NS + 1; constant DELAY_100_US : positive := 100 * 10**3 / CLK_PERIOD_NS + 1; constant DELAY_40_US : positive := 40 * 10**3 / CLK_PERIOD_NS + 1; constant DELAY_NIBBLE : positive := 10**3 / CLK_PERIOD_NS + 1; constant DELAY_LCD_E : positive := 230 / CLK_PERIOD_NS + 1; constant DELAY_SETUP_HOLD : positive := 40 / CLK_PERIOD_NS + 1; constant MAX_DELAY : positive := DELAY_15_MS; -- this record describes one write operation type op_t is record rs : std_logic; data : std_logic_vector(7 downto 0); delay_h : integer range 0 to MAX_DELAY; delay_l : integer range 0 to MAX_DELAY; end record op_t; constant default_op : op_t := (rs => '1', data => X"00", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US); constant op_select_line1 : op_t := (rs => '0', data => X"80", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US); constant op_select_line2 : op_t := (rs => '0', data => X"C0", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US); -- init + config operations: -- write 3 x 0x3 followed by 0x2 -- function set command -- entry mode set command -- display on/off command -- clear display type config_ops_t is array(0 to 5) of op_t; constant config_ops : config_ops_t := (5 => (rs => '0', data => X"33", delay_h => DELAY_4100_US, delay_l => DELAY_100_US), 4 => (rs => '0', data => X"32", delay_h => DELAY_40_US, delay_l => DELAY_40_US), 3 => (rs => '0', data => X"28", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US), 2 => (rs => '0', data => X"06", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US), 1 => (rs => '0', data => X"0C", delay_h => DELAY_NIBBLE, delay_l => DELAY_40_US), 0 => (rs => '0', data => X"01", delay_h => DELAY_NIBBLE, delay_l => DELAY_1640_US)); signal this_op : op_t; type op_state_t is (IDLE, WAIT_SETUP_H, ENABLE_H, WAIT_HOLD_H, WAIT_DELAY_H, WAIT_SETUP_L, ENABLE_L, WAIT_HOLD_L, WAIT_DELAY_L, DONE); signal op_state : op_state_t := DONE; signal next_op_state : op_state_t; signal cnt : natural range 0 to MAX_DELAY; signal next_cnt : natural range 0 to MAX_DELAY; type state_t is (RESET, CONFIG, SELECT_LINE1, WRITE_LINE1, SELECT_LINE2, WRITE_LINE2); signal state : state_t := RESET; signal next_state : state_t; signal ptr : natural range 0 to 15 := 0; signal next_ptr : natural range 0 to 15; begin proc_state : process(state, op_state, ptr, line1_buffer, line2_buffer) is begin case state is when RESET => this_op <= default_op; next_state <= CONFIG; next_ptr <= config_ops_t'high; when CONFIG => this_op <= config_ops(ptr); next_ptr <= ptr; next_state <= CONFIG; if op_state = DONE then next_ptr <= ptr - 1; if ptr = 0 then next_state <= SELECT_LINE1; end if; end if; when SELECT_LINE1 => this_op <= op_select_line1; next_ptr <= 15; if op_state = DONE then next_state <= WRITE_LINE1; else next_state <= SELECT_LINE1; end if; when WRITE_LINE1 => this_op <= default_op; this_op.data <= line1_buffer(ptr*8 + 7 downto ptr*8); next_ptr <= ptr; next_state <= WRITE_LINE1; if op_state = DONE then next_ptr <= ptr - 1; if ptr = 0 then next_state <= SELECT_LINE2; end if; end if; when SELECT_LINE2 => this_op <= op_select_line2; next_ptr <= 15; if op_state = DONE then next_state <= WRITE_LINE2; else next_state <= SELECT_LINE2; end if; when WRITE_LINE2 => this_op <= default_op; this_op.data <= line2_buffer(ptr*8 + 7 downto ptr*8); next_ptr <= ptr; next_state <= WRITE_LINE2; if op_state = DONE then next_ptr <= ptr - 1; if ptr = 0 then next_state <= SELECT_LINE1; end if; end if; end case; end process proc_state; reg_state : process(clk) begin if rising_edge(clk) then if rst = '1' then state <= RESET; ptr <= 0; else state <= next_state; ptr <= next_ptr; end if; end if; end process reg_state; -- we never read from the lcd lcd_rw <= '0'; proc_op_state : process(op_state, cnt, this_op) is begin case op_state is when IDLE => lcd_db <= (others => '0'); lcd_rs <= '0'; lcd_e <= '0'; next_op_state <= WAIT_SETUP_H; next_cnt <= DELAY_SETUP_HOLD; when WAIT_SETUP_H => lcd_db <= this_op.data(7 downto 4); lcd_rs <= this_op.rs; lcd_e <= '0'; if cnt = 0 then next_op_state <= ENABLE_H; next_cnt <= DELAY_LCD_E; else next_op_state <= WAIT_SETUP_H; next_cnt <= cnt - 1; end if; when ENABLE_H => lcd_db <= this_op.data(7 downto 4); lcd_rs <= this_op.rs; lcd_e <= '1'; if cnt = 0 then next_op_state <= WAIT_HOLD_H; next_cnt <= DELAY_SETUP_HOLD; else next_op_state <= ENABLE_H; next_cnt <= cnt - 1; end if; when WAIT_HOLD_H => lcd_db <= this_op.data(7 downto 4); lcd_rs <= this_op.rs; lcd_e <= '0'; if cnt = 0 then next_op_state <= WAIT_DELAY_H; next_cnt <= this_op.delay_h; else next_op_state <= WAIT_HOLD_H; next_cnt <= cnt - 1; end if; when WAIT_DELAY_H => lcd_db <= (others => '0'); lcd_rs <= '0'; lcd_e <= '0'; if cnt = 0 then next_op_state <= WAIT_SETUP_L; next_cnt <= DELAY_SETUP_HOLD; else next_op_state <= WAIT_DELAY_H; next_cnt <= cnt - 1; end if; when WAIT_SETUP_L => lcd_db <= this_op.data(3 downto 0); lcd_rs <= this_op.rs; lcd_e <= '0'; if cnt = 0 then next_op_state <= ENABLE_L; next_cnt <= DELAY_LCD_E; else next_op_state <= WAIT_SETUP_L; next_cnt <= cnt - 1; end if; when ENABLE_L => lcd_db <= this_op.data(3 downto 0); lcd_rs <= this_op.rs; lcd_e <= '1'; if cnt = 0 then next_op_state <= WAIT_HOLD_L; next_cnt <= DELAY_SETUP_HOLD; else next_op_state <= ENABLE_L; next_cnt <= cnt - 1; end if; when WAIT_HOLD_L => lcd_db <= this_op.data(3 downto 0); lcd_rs <= this_op.rs; lcd_e <= '0'; if cnt = 0 then next_op_state <= WAIT_DELAY_L; next_cnt <= this_op.delay_l; else next_op_state <= WAIT_HOLD_L; next_cnt <= cnt - 1; end if; when WAIT_DELAY_L => lcd_db <= (others => '0'); lcd_rs <= '0'; lcd_e <= '0'; if cnt = 0 then next_op_state <= DONE; next_cnt <= 0; else next_op_state <= WAIT_DELAY_L; next_cnt <= cnt - 1; end if; when DONE => lcd_db <= (others => '0'); lcd_rs <= '0'; lcd_e <= '0'; next_op_state <= IDLE; next_cnt <= 0; end case; end process proc_op_state; reg_op_state : process (clk) is begin if rising_edge(clk) then if state = RESET then op_state <= IDLE; else op_state <= next_op_state; cnt <= next_cnt; end if; end if; end process reg_op_state; end architecture rtl;

โค๊ด  LCD 

------------------------------------------------------------------------------- -- Title : Synthesizable demo for design "lcd16x2_ctrl" -- Project : ------------------------------------------------------------------------------- -- File : lcd16x2_ctrl_tb.vhd -- Author : <stachelsau@T420> -- Company : -- Created : 2012-07-28 -- Last update: 2012-07-29 -- Platform : -- Standard : VHDL'93/02 ------------------------------------------------------------------------------- -- Description: This demo writes writes a "hello world" to the display and -- interchanges both lines periodically. ------------------------------------------------------------------------------- -- Copyright (c) 2012 ------------------------------------------------------------------------------- -- Revisions : -- Date Version Author Description -- 2012-07-28 1.0 stachelsau Created ------------------------------------------------------------------------------- library ieee; use ieee.std_logic_1164.all; ------------------------------------------------------------------------------- entity LCD is port ( clk : in std_logic; lcd_e : out std_logic; lcd_rs : out std_logic; lcd_rw : out std_logic; lcd_db : out std_logic_vector(7 downto 4)); end entity LCD; ------------------------------------------------------------------------------- architecture behavior of LCD is -- signal timer : natural range 0 to 100000000 := 0; signal switch_lines : std_logic := '0'; signal line1 : std_logic_vector(127 downto 0); signal line2 : std_logic_vector(127 downto 0); -- component generics constant CLK_PERIOD_NS : positive := 10; -- 100 Mhz -- component ports signal rst : std_logic; signal line1_buffer : std_logic_vector(127 downto 0); signal line2_buffer : std_logic_vector(127 downto 0); begin -- architecture behavior -- component instantiation DUT : entity work.lcd16x2_ctrl generic map ( CLK_PERIOD_NS => CLK_PERIOD_NS) port map ( clk => clk, rst => rst, lcd_e => lcd_e, lcd_rs => lcd_rs, lcd_rw => lcd_rw, lcd_db => lcd_db, line1_buffer => line1_buffer, line2_buffer => line2_buffer); rst <= '0'; -- see the display's datasheet for the character map line1(127 downto 120) <= X"20"; line1(119 downto 112) <= X"20"; line1(111 downto 104) <= X"48"; -- H line1(103 downto 96) <= X"65"; -- e line1(95 downto 88) <= X"6c"; -- l line1(87 downto 80) <= X"6c"; -- l line1(79 downto 72) <= X"6f"; -- o line1(71 downto 64) <= X"20"; line1(63 downto 56) <= X"57"; -- W line1(55 downto 48) <= X"6f"; -- o line1(47 downto 40) <= X"72"; -- r line1(39 downto 32) <= X"6c"; -- l line1(31 downto 24) <= X"64"; -- d line1(23 downto 16) <= X"21"; -- ! line1(15 downto 8) <= X"20"; line1(7 downto 0) <= X"20"; line2(127 downto 120) <= X"30"; line2(119 downto 112) <= X"31"; line2(111 downto 104) <= X"32"; line2(103 downto 96) <= X"33"; line2(95 downto 88) <= X"34"; line2(87 downto 80) <= X"35"; line2(79 downto 72) <= X"36"; line2(71 downto 64) <= X"37"; line2(63 downto 56) <= X"38"; line2(55 downto 48) <= X"39"; line2(47 downto 40) <= X"3a"; line2(39 downto 32) <= X"3b"; line2(31 downto 24) <= X"3c"; line2(23 downto 16) <= X"3d"; line2(15 downto 8) <= X"3e"; line2(7 downto 0) <= X"3f"; line1_buffer <= line2 when switch_lines = '1' else line1; line2_buffer <= line1 when switch_lines = '1' else line2; -- switch lines every second process(clk) begin if rising_edge(clk) then if timer = 0 then timer <= 100000000; switch_lines <= not switch_lines; else timer <= timer - 1; end if; end if; end process; end architecture behavior;

ผลการทดลอง

LAB UART [temp]

การทดลองที่ 6

Serial UART

อุปกรณ์

1. บอร์ด Altena Cyclone III                                                                                                        1 บอร์ด

2. สายดาวน์โหลด ByteBlaster II Cable หรือ สายดาวน์โหลดUSB Blaster Cable                                1 ชุด

3. เครื่องคอมพิวเตอร์(Quatus II web edition)                                                                           

4. ออสซิลโลสโคป                                                                                                                      1เครื่อง

5. โปรแกรม Putty       
          

โจทย์

สร้างวงจรดิจิทัลเพื่อส่งตัวอักษร 'a' ผ่าน UART ไปยังคอมพิวเตอร์ เมื่อกดปุ่มแล้วปล่อยในแต่ละครั้ง โดยใช้ค่า baudrate เท่ากับ 9600 (เน้นส่งข้อมูลไบต์จาก FPGA ไปยังคอมพิวเตอร์เท่านั้น ยังไม่ต้องรับข้อมูล)

Source Code 

โค๊ด  component_debounce

library ieee; library work; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity component_debounce is generic( DELAY: integer :=20000 ); port( CLK, PB : in std_logic; signal_out : out std_logic ); end component_debounce; architecture Behavior of component_debounce is signal debounce,latch: integer:=0; signal pressed,signal_sent: std_logic:='1'; begin process (CLK, PB) begin if rising_edge(CLK) then if(PB = '1')then debounce <= 0; latch <= latch + 1; if latch > 10000 then signal_sent <= '1'; end if; else debounce <= debounce + 1; latch <= 0; end if; if(debounce > DELAY)then pressed <= '1'; end if; if(pressed = '1')and(PB = '1')then signal_sent <= '0'; pressed <= '0'; end if; end if; end process; signal_out <= signal_sent; end Behavior;

โค๊ด uart_lib

--===========================================================================-- -- -- S Y N T H E Z I A B L E miniUART C O R E -- -- www.OpenCores.Org - January 2000 -- This core adheres to the GNU public license -- -- Design units : UART_Def -- -- File name : uart_lib.vhd -- -- Purpose : Implements an miniUART device for communication purposes -- between the OR1K processor and the Host computer through -- an RS-232 communication protocol. -- -- Library : uart_lib.vhd -- -- Dependencies : IEEE.Std_Logic_1164 -- --===========================================================================-- ------------------------------------------------------------------------------- -- Revision list -- Version Author Date Changes -- -- 0.1 Ovidiu Lupas 15 January 2000 New model -- olupas@opencores.org ------------------------------------------------------------------------------- -------------------------------------------------------------------------------- -- package UART_Def -------------------------------------------------------------------------------- library IEEE,STD; use IEEE.Std_Logic_1164.all; use IEEE.Numeric_Std.all; --**-- package UART_Def is ----------------------------------------------------------------------------- -- Converts unsigned Std_LOGIC_Vector to Integer, leftmost bit is MSB -- Error message for unknowns (U, X, W, Z, -), converted to 0 -- Verifies whether vector is too long (> 16 bits) ----------------------------------------------------------------------------- function ToInteger ( Invector : in Unsigned(3 downto 0)) return Integer; end UART_Def; --==================== End of package header ======================-- package body UART_Def is function ToInteger ( InVector : in Unsigned(3 downto 0)) return Integer is constant HeaderMsg : String := "To_Integer:"; constant MsgSeverity : Severity_Level := Warning; variable Value : Integer := 0; begin for i in 0 to 3 loop if (InVector(i) = '1') then Value := Value + (2**I); end if; end loop; return Value; end ToInteger; end UART_Def; --================ End of package body ================--

โค๊ด UART_comp

library ieee,work; use ieee.std_logic_1164.all; use ieee.numeric_std.all; use IEEE.STD_LOGIC_ARITH.ALL; use IEEE.STD_LOGIC_UNSIGNED.ALL; entity UART_comp is port ( CLK : in Std_Logic; -- System Clock -- Rx : out Std_Logic; -- Control signal TxOut : out Std_Logic; -- Control signal PB : in Std_Logic:= '1'; Reset : in Std_Logic); -- Reset input end entity; --================== End of entity ==============================-- architecture Behaviour of UART_comp is component clkUnit port( SysClk : in Std_Logic; -- System Clock EnableRx : out Std_Logic; -- Control signal EnableTx : out Std_Logic; -- Control signal Reset : in Std_Logic -- Reset input ); end component; component component_debounce generic( DELAY: integer :=20000 ); port( CLK, PB : in std_logic; signal_out : out std_logic ); end component; signal tx_rdy : std_logic :='1'; --indicator signal t_tx : Std_Logic:= '0'; --buffer type tx_state_type is (IDLE,START,SEND,STOP); --state signal state : tx_state_type :=IDLE; signal s_stop,t_sig: std_logic:= '0'; --stop sending signal s_start : std_logic; -- still sending signal s_sent : std_logic:='1'; -- still sending signal data_count : integer :=0; --array counter signal s_EnableRx,s_EnableTx : std_logic; -- tx/rx tick signal signal data_out :std_logic_vector (7 downto 0):=(x"41"); --designed data out signal data_1 :std_logic_vector (7 downto 0):=(x"01"); --designed data out begin cmp1_inst: clkUnit port map(SysClk => CLK, EnableRx => s_EnableRx, EnableTx => s_EnableTx ,Reset => Reset ); --end generate; cmp2_inst: component_debounce port map(CLK => CLK, PB => PB,signal_out => s_sent); process (CLK , Reset) begin if Reset = '0' then state <= idle; t_tx <='1'; data_out <= x"41"; elsif rising_edge(CLK) then case state is when IDLE => s_stop <= '0'; s_start <= '0'; t_tx <= '1'; if s_sent = '0' then if s_EnableTx = '1' then t_tx <= '0'; state <= START; s_start <= '1'; end if; else state <= IDLE; end if; when START => if s_start = '1' then state <= SEND; else state <= START; end if; when SEND => s_start <= '0'; if s_EnableTx = '1' then if s_stop = '0' and data_count < 8 then t_Tx <= data_out(data_count); if t_sig = '1' then data_count <= data_count +1; t_sig <='0'; end if; elsif data_count >= 8 then t_tx <= '1'; s_stop <= '1'; state <= STOP; end if; else state <= SEND; t_sig <= '1'; end if; when STOP => data_count <= 0; if s_EnableTx = '1' then if s_stop = '1' then t_tx <= '1'; s_stop <= '0'; else state <= IDLE; data_out <= data_out + "1"; end if; else state <= STOP; end if; end case; end if; end process; TXout <= t_TX; end Behaviour; --==================== End of architecture ===================--

โค๊ด TB_UART_comp

library ieee; library work; use ieee.std_logic_1164.all; use ieee.std_logic_arith.all; use ieee.numeric_std.all; entity TB_UART_comp is end TB_UART_comp; architecture testbench of TB_UART_comp is component UART_comp is port( CLK,Reset,PB : in std_logic; TxOut : out std_logic ); end component; signal t_CLK,t_Reset,t_TxOut,t_PB: std_logic; begin inst:UART_comp port map (CLK => t_CLK, Reset => t_Reset, TxOut=> t_TxOut ,PB =>t_PB ); process begin -- a process for generating the clock signal (50MHz) t_CLK <= '1'; wait for 10 ns; t_CLK <= '0'; wait for 10 ns; end process; process begin -- a process for generating the clock signal (50MHz) t_PB <= '1'; wait for 2 ms; t_PB <= '0'; wait for 2 ms; t_PB <= '1'; wait for 2 ms; t_PB <= '0'; wait for 2 ms; wait; end process; process begin t_Reset <= '1'; wait for 5 ms;t_Reset <= '0'; wait for 1 ms;t_Reset <= '1'; wait; end process; end testbench;

โค๊ด ClkUnit

library ieee; use ieee.std_logic_1164.all; use ieee.numeric_std.all; library work; ------------------------------------------------------------------------------- -- Baud rate generator ------------------------------------------------------------------------------- entity ClkUnit is port ( SysClk : in Std_Logic; -- System Clock EnableRx : out Std_Logic; -- Control signal EnableTx : out Std_Logic; -- Control signal Reset : in Std_Logic); -- Reset input end entity; --================== End of entity ==============================-- ------------------------------------------------------------------------------- -- Architecture for Baud rate generator Unit ------------------------------------------------------------------------------- architecture Behaviour of ClkUnit is ----------------------------------------------------------------------------- -- Signals ----------------------------------------------------------------------------- signal ClkDiv32 : Std_Logic; signal tmpEnRX : Std_Logic; signal tmpEnTX : Std_Logic; signal Cnt32,Cnt10,Cnt16 : integer:=0; begin ----------------------------------------------------------------------------- -- Divides the system clock of 50 MHz by 32 ----------------------------------------------------------------------------- process(SysClk,Reset) begin if Rising_Edge(SysClk) then if Reset = '0' then Cnt32 <= 0; ClkDiv32 <= '0'; else Cnt32 <= Cnt32 + 1; if Cnt32 = 32 then ClkDiv32 <= '1'; Cnt32 <= 0; -- 26 ns? else ClkDiv32 <= '0'; end if; end if; end if; end process; ----------------------------------------------------------------------------- -- Provides the EnableRX signal, at ~ 155 KHz ----------------------------------------------------------------------------- process(SysClk,Reset) begin if Rising_Edge(SysClk) then if Reset = '0' then Cnt10 <= 0; tmpEnRX <= '0'; elsif ClkDiv32 = '1' then Cnt10 <= Cnt10 + 1; end if; if Cnt10 = 10 then tmpEnRX <= '1'; Cnt10 <=0; else tmpEnRX <= '0'; end if; end if; end process; ----------------------------------------------------------------------------- -- Provides the EnableTX signal, at 9.6 KHz ----------------------------------------------------------------------------- process(SysClk,Reset) begin if Rising_Edge(SysClk) then if Reset = '0' then Cnt16 <= 0; tmpEnTX <= '0'; elsif tmpEnRX = '1' then Cnt16 <= Cnt16 + 1; end if; if Cnt16 = 15 then tmpEnTX <= '1'; Cnt16 <= Cnt16 + 1; elsif Cnt16 = 17 then Cnt16 <= 0; tmpEnTX <= '0'; else tmpEnTX <= '0'; end if; end if; end process; EnableRX <= tmpEnRX; EnableTX <= tmpEnTX; end Behaviour; --==================== End of architecture ===================--

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