High Levels Logics Design: กุมภาพันธ์ 2015

การทดลองที่ 3

component

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1. บอร์ด xilinx 1 บอร์ด

2. สายดาวน์โหลด ByteBlaster II Cable หรือ สายดาวน์โหลดUSB Blaster Cable 1 ชุด

3. เครื่องคอมพิวเตอร์(Quatus II web edition) 1ชุด

4. ออสซิลโลสโคป 1เครื่อง

5. WS2812 RGB LED 1ดวง

โจทย์

ให้นศ.นำวงจรเดิม (WS2812 RGB LED) ที่ได้ออกแบบไว้ด้วยภาษา VHDL มาแก้ไข โดยแบ่งวงจรเดิม (design partitioning) ในระดับ top-level design ให้มีหรือประกอบด้วย component อย่างน้อย 3 ส่วน และออกแบบแต่ละส่วน ให้สามารถนำกลับมาใช้ได้อีก (design for reuse) และเมื่อนำมาร่วมกัน ยังสามารถทำงานได้ตามเดิม อธิบายการทำงานของแต่ละส่วนว่า มีอินเทอร์เฟส (interface) หลักการทำงาน และใช้เพื่อวัตถุประสงค์ในวงจร + การจำลองการทำงาน (Simulation) ของแต่ละส่วนด้วย VHDL Testbench (Unit Testing) และใช้ VHDL testbench เดิมทดสอบระบบรวม (Integration Testing)

โค๊ด component debounce

โค๊ด testbench ของ component debounce

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity TB_component_debounce is
end TB_component_debounce;

architecture testbench of TB_component_debounce is
  component component_debounce is
 port(
  CLK, PB : in std_logic;
  signal_out : out std_logic
 );
    end component;

signal t_CLK,t_signal_out,t_PB  : std_logic;

begin
  
  inst:component_debounce port map (CLK => t_CLK, signal_out => t_signal_out ,PB => t_PB );
  
  process begin -- a process for generating the clock signal (50MHz) 
    t_CLK <= '1'; wait for 10 ns;
    t_CLK <= '0'; wait for 10 ns;
  end process;

process begin -- a process for generating the UP input signal 
    t_PB <= '1' ;wait for 0.5 ms;
  t_PB <= '0' ;wait for 0.5 ms;
  t_PB <= '1' ;wait for 0.5 ms;
  t_PB <= '0' ;wait for 0.5 ms;
  t_PB <= '1' ;wait for 0.5 ms;
  t_PB <= '0' ;wait for 0.5 ms;
  t_PB <= '1' ;wait for 0.5 ms;
    t_PB <= '0' ;wait for 0.5 ms;
  t_PB <= '1' ;wait for 5 ms;
 end process;
end testbench;

โค๊ด component data

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity component_DATA is
 port(
 CLK : in std_logic;
 input_data : in std_logic_vector (23 downto 0) := x"000000"; 
 data_out : out std_logic
 );
end component_DATA;

architecture Behavior of component_DATA is
 signal duty_bit,i,duty_t: integer:=0;
 signal data_t: std_logic_vector(23 downto 0):=x"000000";
 signal data_send,sended: std_logic:='0';
begin
process (CLK) begin     
   if rising_edge(CLK) then    
    if(data_t /= input_data) then 
     sended <= '0';
    -- send_state <= '0';
     data_t <= input_data;
    end if;
           
    if sended = '0' then
     if duty_t < 4250 then  
      duty_t <= duty_t +1;     
      if duty_t < 1536 then --30.072us
       if i < 24 then
        if data_t(i) = '0' then 
         if duty_bit < 57 then
          duty_bit <= duty_bit +1;
          if duty_bit < 18 then
           data_send <= '1';  
          else
           data_send <= '0';  
          end if;
         else
          duty_bit <= 0;
          i <= i+1;   
         end if; 
        elsif data_t(i) = '1' then 
         if duty_bit < 65 then
          duty_bit <= duty_bit +1;
          if duty_bit < 35 then
           data_send <= '1';  
          else
           data_send <= '0';  
          end if;
         else
          duty_bit <= 0; 
          i <= i+1;   
         end if;
        end if;
       end if;
      else
       data_send <= '0';  
       i<=0;
       duty_bit <=0;
      end if;  
     else
      duty_t <= 0;
      sended <= '1';
     end if;
    end if;   
   end if; 
end process;
 data_out <= data_send;
end Behavior;

โค๊ด testbench ของ component data

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity TB_Component_DATA is
end TB_Component_DATA;

architecture testbench of TB_component_DATA is
  component Component_DATA is
 port(
  CLK: in std_logic;
  input_data : in std_logic_vector (23 downto 0) := x"000000"; 
  data_out : out std_logic
  );
   end component;

signal t_CLK,t_data_out: std_logic; 
  signal t_input_data : std_logic_vector (23 downto 0);

begin
  
  inst:Component_DATA port map (CLK => t_CLK, data_out => t_data_out ,input_data => t_input_data );
  
  process begin -- a process for generating the clock signal (50MHz) 
    t_CLK <= '1'; wait for 10 ns;
    t_CLK <= '0'; wait for 10 ns;
  end process;

--  process begin -- a process for generating the UP input signal 
--    t_input_sended <= '1' ;wait for 0.5 ms;
--  t_input_sended <= '0' ;wait for 0.5 ms;
--  t_input_sended <= '1' ;wait for 0.5 ms;
--  t_input_sended <= '0' ;wait for 0.5 ms;
--  t_input_sended <= '1' ;wait for 0.5 ms;
--  t_input_sended <= '0' ;wait for 0.5 ms;
--  t_input_sended <= '1' ;wait for 0.5 ms;
--    t_input_sended <= '0' ;wait for 0.5 ms;
--  t_input_sended <= '1' ;wait for 5 ms;
-- end process;
  process begin -- a process for generating the UP input signal 
    t_input_data <= x"000000" ;wait for 1 ms;
  t_input_data <= x"0000FF" ;wait for 1 ms;
  t_input_data <= x"00FF00" ;wait for 1 ms;
  t_input_data <= x"FF0000" ;wait for 1 ms;
 end process;
 
 
end testbench;

โค๊ด component fsm

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity component_fsm is
 generic(
  icolor : integer :=4
 );
 port(
  CLK,input_change,input_reset : in std_logic;
  data_out : out std_logic_vector(23 downto 0)
 );
end component_fsm;

architecture FSM of component_fsm is
 type rgb_mem is array (0 to icolor-1) of std_logic_vector(23 downto 0);
 constant rgb_color :rgb_mem :=(
 0 => x"000000" , 1 => x"0000FF", 
 2 => x"00FF00" , 3 => x"FF0000"); 
 type state_type is (S0,S1,S2,S3);
 signal state : state_type :=S0;
 signal data_t: std_logic_vector(23 downto 0):=rgb_color(0);
 signal signal_t : std_logic:= '0';
begin
process (CLK, input_change,input_reset) begin     
   if input_reset = '0' then
    state <= S0;
    data_t <= x"000000";
   elsif rising_edge(CLK) then 
    case state is
      when S0 =>
       data_t <= rgb_color(0);
       if input_change = '1' and signal_t = '1' then 
        state <=S1;
        signal_t <= '0';
       elsif input_change = '1' and signal_t = '0' then
        state <= S0; 
       elsif input_change = '0' and signal_t = '0' then
        signal_t <= '1';
        state <= S0;
       end if;
      when S1 =>
       data_t <= rgb_color(1);
       if input_change = '1' and signal_t = '1' then 
        state <=S2;
        signal_t <= '0';
       elsif input_change = '1' and signal_t = '0' then
        state <= S1; 
       elsif input_change = '0' and signal_t = '0' then
        signal_t <= '1';
        state <= S1;
       end if;
      when S2 =>
       data_t <= rgb_color(2);
       if input_change = '1' and signal_t = '1' then 
        state <=S3;
        signal_t <= '0';
       elsif input_change = '1' and signal_t = '0' then
        state <= S2; 
       elsif input_change = '0' and signal_t = '0' then
        signal_t <= '1';
        state <= S2;
       end if;
      when S3 =>
       data_t <= rgb_color(3);
       if input_change = '1' and signal_t = '1' then 
        state <=S0;
        signal_t <= '0';
       elsif input_change = '1' and signal_t = '0' then
        state <= S3; 
       elsif input_change = '0' and signal_t = '0' then
        signal_t <= '1';
        state <= S3;
       end if;
--      when RESET =>
--       data_t <= x"000000"; 
--       if input_change = '1' and signal_t = '1' then 
--        state <=S1;
--        signal_t <= '0';
--       elsif input_change = '1' and signal_t = '0' then
--        state <= RESET; 
--       elsif input_change = '0' and signal_t = '0' then
--        signal_t <= '1';
--        state <= RESET;
--       else 
--        state <= RESET; 
--       end if;        
      end case; 
    end if; 
end process;
 data_out <= data_t;
end FSM;

โค๊ด testbench ของ component fsm

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity TB_component_fsm is
end TB_component_fsm;

architecture testbench of TB_component_fsm is
  component component_fsm is
 port(
  CLK,input_change,input_reset: in std_logic;
  --signal_out : out std_logic;
  data_out : out std_logic_vector(23 downto 0)
 );
    end component;

signal t_CLK,t_signal_out,t_input_change,t_input_reset  : std_logic; 
  signal t_data_out  : std_logic_vector(23 downto 0);

begin
  
  inst:component_fsm port map (CLK => t_CLK, data_out => t_data_out ,
  input_reset => t_input_reset,input_change => t_input_change);
  
  process begin -- a process for generating the clock signal (50MHz) 
    t_CLK <= '1'; wait for 10 ns;
    t_CLK <= '0'; wait for 10 ns;
  end process;

process begin -- a process for generating the UP input signal 
    t_input_change <= '0' ;wait for 0.5 ms;
  t_input_change <= '1' ;wait for 20  ns;
  t_input_change <= '0' ;wait for 0.5 ms;
  t_input_change <= '1' ;wait for 20  ns;
  t_input_change <= '0' ;wait for 0.5 ms;
  t_input_change <= '1' ;wait for 20  ns;
  t_input_change <= '0' ;wait for 0.5 ms;
  t_input_change <= '1' ;wait for 20  ns;
    t_input_change <= '0' ;wait for 5 ms;
  t_input_change <= '1' ;wait for 3 ms;

end process;
 
-- process begin -- a process for generating the UP input signal 
--    t_input_state <= '0' ;wait for 0.5 ms;
--  wait for 20 ns;
--  t_input_state <= '1' ;wait for 20  ns;
--  t_input_state <= '0' ;wait for 0.5 ms;
--  t_input_state <= '1' ;wait for 20  ns;
--  t_input_state <= '0' ;wait for 0.5 ms;
--  t_input_state <= '1' ;wait for 20  ns;
--  t_input_state <= '0' ;wait for 0.5 ms;
--  t_input_state <= '1' ;wait for 20  ns;
--  t_input_state <= '0' ;wait for 5 ms;
--  
-- end process;
 
 process begin -- a process for generating the UP input signal 
    t_input_reset <= '0' ;
  wait for 2 ms;
  t_input_reset <= '1' ;wait for 20  ns;
  t_input_reset <= '0' ;wait for 5  ms;
 end process;
end testbench;

โค๊ดรวม RGB component

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity RGB_com is
 port(
  CLK, PB,RESET : in std_logic;
  DATA_out : out std_logic
 );
end RGB_com;

architecture structural of RGB_com is
 
 component component_debounce 
 port(
  CLK : in std_logic;
  PB : in std_logic;
  signal_out : out std_logic
 );
 end component;
 
 component component_fsm 
 port(
  CLK,input_change,input_reset : in std_logic;
  data_out : out std_logic_vector(23 downto 0)
 );
 end component;
 
 component component_DATA is
 port(
 CLK : in std_logic;
 input_data : in std_logic_vector (23 downto 0) := x"000000"; 
 data_out : out std_logic
 );
 end component;

--signal p_input_change: std_logic; -- component Component_DATA is
 signal p_data_out_24: std_logic_vector(23 downto 0); -- component Component_DATA is
 signal p_signal_out: std_logic;
-- port(
--  CLK,input_sended : in std_logic;
--  input_data : in std_logic_vector (23 downto 0) := x"000000"; 
--  data_sended : out std_logic;
--  data_out : out std_logic
--  );
--   end component;
--

begin
 
 cmp1_inst: component_debounce 
 port map(CLK => CLK, PB => PB,signal_out => p_signal_out);
 --end generate;
  
 cmp2_inst: component_fsm 
 port map(CLK => CLK, input_reset => RESET , input_change => p_signal_out  , data_out => p_data_out_24  );
 
 cmp3_inst: component_Data
 port map(CLK => CLK, input_data => p_data_out_24, data_out => DATA_out);
 
 
 
              
 
end structural;

โค๊ด testbench ของ RGB component

library ieee;
library work;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
use ieee.numeric_std.all;

entity TB_RGB_com is
end TB_RGB_com;

architecture testbench of TB_RGB_com is
  component RGB_com is
 port(
  CLK, PB,RESET : in std_logic;
  DATA_out : out std_logic
 );
   end component;

signal t_CLK,t_PB,t_RESET,t_data_out: std_logic;

begin
  
  inst:RGB_com port map (CLK => t_CLK, data_out => t_data_out ,PB => t_PB ,RESET => t_RESET );
  
  process begin -- a process for generating the clock signal (50MHz) 
    t_CLK <= '1'; wait for 10 ns;
    t_CLK <= '0'; wait for 10 ns;
  end process;
 
  process begin -- a process for generating the clock signal (50MHz) 
    t_RESET <= '1'; wait for 5 ms;
  t_RESET <= '0'; wait for 3 ms;
    t_RESET <= '1'; wait for 10 ms;
  end process;

process begin -- a process for generating the clock signal (50MHz) 
    t_PB <= '1'; wait for 2 ms;
  t_PB <= '0'; wait for 0.5 ms;
    t_PB <= '1'; wait for 0.5 ms;
  t_PB <= '0'; wait for 0.5 ms;
    t_PB <= '1'; wait for 0.5 ms;
  end process;
 
 
end testbench;

ผลการทดลอง

High Levels Logics Design

วันเสาร์ที่ 21 กุมภาพันธ์ พ.ศ. 2558

LAB 3 component

การทดลองที่ 3

component

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